Transistor Level Implementation of Cyclic Combinational Circuits

Combinational Circuits are defined as the circuit whose output depends on present inputs only and are memory less.Thesecircuits are generally acyclic (feed-forward) but cyclic circuits can be combinational where cycles sometimes occur in designs synthesized from high-level descriptions. Feedbackinsuch cases is carefully contrived when functional units are connected in a cyclic topology. Deliberate incorporation of such cycles or feedbacks in conventional combinational circuit eventually results in less number of transistor counts leading to improved speed and power performance.So a Cyclic Combinational Circuit is defined as the circuit whose output depends on present inputs only,but at the same time contains one or more topological feedback paths. In this paper, we argue the case for radically rethinking the concept of combinational circuit design. We should no longer think of combinational logic as acyclic in theory or in practice since nearlyall combinational circuits are best designed with cycles. We propose a methodology and demonstrate the samewith a test case for the synthesis of some popular combinational circuits like 2-Bit Magnitude Comparator. A feedback was introduced in the substitution or minimization phase optimizing a multilevel network description for area or transistor count and specially static anddynamic power consumption. The simulations were carried out using the standard Cadence Virtuoso Suite.Further the optimized cyclic combinational circuit is implemented in ASIC platform using Cadence Layout XLSuite and design verification was done using ASSURA DRC and LVS Verification Tool. The test runs confirmed the transistor level functioning of the optimized layout. In simulations, transistor count was minimized significantly leading to 34%, 14% and 26% savings in the area, dynamic and static power respectivelyas compared to the conventional implementation technique.